MT48LC128M4A2P-7ELITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-7ELITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 43: READ – Full-Page Burst
T0
CLK
tCKS tCKH
CKE
T1
tCL
tCH
tCMS tCMH
COMMAND
ACTIVE
NOP
T2
tCK
READ
DQM/
DQML, DQMH
tCMS tCMH
A0–A9,
A11, A12
tAS tAH
ROW
tAS tAH
A10
ROW
BA0, BA1
tAS tAH
BANK
COLUMN m 2
BANK
T3
NOP
DQ
tRCD
tAC
tLZ
CAS Latency
T4
NOP
T5
NOP
T6
( ( Tn + 1
))
((
))
((
))
((
))
((
))
NOP ( (
))
((
))
((
))
NOP
Tn + 2
Tn + 3
BURST TERM
NOP
((
))
((
))
((
))
((
))
((
))
((
))
tAC
tOH
DOUT m
tAC
tOH
DOUT m+1
tAC ( (
tOH ) )
((
))
DOUT m+2( (
))
tAC
tOH
DOUT m-1
1,024 (x16) locations within same row
2,048 (x8) locations within same row
4,096 (x4) locations within same row
tAC
tOH
Dout m
tOH
DOUT m+1
tHZ
Tn + 4
NOP
Full page completed
Full-page burst does not self-terminate.
Can use BURST TERMINATE command. 3
Don’t Care
Undefined
Notes:
1. For this example, CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
3. Page left open; no tRP.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
59
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