MT48LC16M4A2 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC16M4A2' PDF : 55 Pages View PDF
NOTES
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V;
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.
3. IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C £ TA £ +70°C and
-40°C £ TA £ +85°C for IT parts) is ensured.
6. An initial pause of 100µs is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD
and VDDQ must be powered up simultaneously. VSS
and VSSQ must be at same potential.) The two
AUTO REFRESH command wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between VIH
and VIL (or between VIL and VIH) in a monotonic
manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V,
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1 ns, then
the timing is referenced at VIL (MAX) and VIH (MIN)
and no longer at the 1.5V crossover point. CLK
should always be 1.5V referenced to crossover. Re-
fer to Micron Technical Note TN-48-09
12. Other input signals are allowed to transition no
more than once every two clocks and are otherwise
at valid VIH or VIL levels.
64Mb: x4, x8, x16
SDRAM
13. IDD specifications are tested after the device is prop-
erly initialized.
14. Timing actually specified by tCKS; clock(s) speci-
fied as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any timing param-
eter.
18. The IDD current will increase or decrease propor-
tionally according to the amount of frequency al-
teration for the test condition.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times dur-
ing this period.
21. Based on tCK = 10ns for -8E , tCK=7.5ns for -75
and -7E, tCK = 6ns for -6.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width £ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width £ 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during ac-
cess or precharge states (READ, WRITE, including
tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (tRP) begins 6ns/7ns/7.5ns/7ns after the
first clock delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is
guaranteed by design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -8E, CL = 2 and tCK = 10ns; for -75, CL = 3 and
tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns; for -6,
CL = 3 and tCK = 6ns.
33. CKE is HIGH during refresh command period
tRFC (MIN) else CKE is LOW. The IDD6 limit is actu-
ally a nominal value and does not result in a fail
value.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
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