MT48LC16M4A2 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC16M4A2' PDF : 55 Pages View PDF
64Mb: x4, x8, x16
SDRAM
POWER-DOWN MODE 1
T0
CLK
T1
tCK
T2
tCL
((
))
tCH
tCKS
((
))
CKE
((
tCKS tCKH
))
tCMS tCMH
((
COMMAND PRECHARGE
NOP
NOP
))
((
))
((
DQM /
))
DQML, DQMH
((
))
((
A0-A9, A11
))
((
))
ALL BANKS
((
A10
))
((
SINGLE BANK
))
tAS tAH
((
BA0, BA1
BANK(S)
))
((
))
High-Z
DQ
Precharge all
active banks
Two clock cycles
All banks idle, enter
power-down mode
((
))
Input buffers gated off while in
power-down mode
Exit power-down mode
Tn + 1
tCKS
Tn + 2
NOP
ACTIVE
ROW
ROW
BANK
All banks idle
DON’T CARE
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK(3)
-6
-7E
-75
-8E
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1
0.8
0.8
1
ns
1.5
1.5
1.5
2
ns
2.5
2.5
2.5
3
ns
2.5
2.5
2.5
3
ns
6
7
7.5
8
ns
SYMBOL*
tCK(2)
tCKH
tCKS
tCMH
tCMS
-6
-7E
-75
-8E
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
–
7.5
10
10
ns
1
0.8
0.8
1
ns
1.5
1.5
1.5
2
ns
1
0.8
0.8
1
ns
1.5
1.5
1.5
2
ns
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
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