MT48LC32M16A2P-7ELITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC32M16A2P-7ELITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Operations
Figure 29: READ with Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ - AP
BANK n
NOP
NOP
BANK n
Page
Active
READ with Burst of 4
Internal
States
BANK m
Page Active
NOP
WRITE - AP
NOP
NOP
BANK m
Interrupt Burst, Precharge
tRP - BANK n
WRITE with Burst of 4
NOP
Idle
t WR - BANK m
Write-Back
ADDRESS
1
DQM
BANK n,
COL a
DQ
CL = 3 (BANK n)
BANK m,
COL d
DOUT
DIN
a
d
DIN
d+1
DIN
d+2
DIN
d+3
Transitioning Data
Don’t Care
Notes: 1. DQM is HIGH at T2 to prevent DOUT - a + 1 from contending with DIN - d at T4.
WRITE with Auto Precharge
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ
to bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (see Figure 30).
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (see Figure 31 on page 37).
Figure 30: WRITE with Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
WRITE - AP
BANK n
NOP
READ - AP
NOP
BANK m
NOP
NOP
BANK n
Internal
States
BANK m
Page Active
WRITE with Burst of 4
Page Active
Interrupt Burst, Write-Back
tWR - BANK n
Precharge
tRP - BANK n
READ with Burst of 4
NOP
tRP - BANK m
ADDRESS
DQ
BANK n,
COL a
DIN
a
DIN
a+1
Note: DQM is LOW.
BANK m,
COL d
DOUT
d
CL = 3 (BANK m)
Transitioning Data
DOUT
d+1
Don’t Care
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
36
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