MT48LC4M32B2B5-6AAT View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC4M32B2B5-6AAT' PDF : 79 Pages View PDF
Figure 29: WRITE-to-PRECHARGE
T0
CLK
tWR @ tCK ≥ 15ns
DQM
Command
WRITE
Address
Bank a,
Col n
DQ
DIN
T1
T2
T3
T4
NOP
PRECHARGE
tRP
NOP
NOP
Bank
(a or all)
tWR
DIN
128Mb: x32 SDRAM
WRITE Operation
T5
T6
ACTIVE
NOP
Bank a,
Row
tWR @ tCK < 15ns
DQM
Command
WRITE
NOP
Address
Bank a,
Col n
DQ
DIN
DIN
NOP
PRECHARGE
tRP
NOP
NOP
Bank
(a or all)
t WR
ACTIVE
Bank a,
Row
Transitioning data
Don’t Care
Note: 1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command is ignored. The last data written (provided that DQM is LOW at
that time) will be the input data applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 30 (page 56), where data n is the last desired data
element of a longer burst.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
55
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© 2001 Micron Technology, Inc. All rights reserved.
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