MT48LC4M32B2B5-7 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC4M32B2B5-7' PDF : 79 Pages View PDF
128Mb: x32 SDRAM
Electrical Specifications – IDD Parameters
8. The IDD current will decrease as CL is reduced. This is due to the fact that the maximum
cycle rate is slower as CL is reduced.
9. JEDEC and PC100 specify three clocks.
10. AC timing and IDD tests have VIL = 0.25 and VIH = 2.75, with timing referenced to the
1.5V crossover point.
11. Enables on-chip refresh and address counters.
12. CKE is HIGH during refresh command period tRFC (MIN), or else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
19
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