MT48LC4M32B2B5-7 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC4M32B2B5-7' PDF : 79 Pages View PDF
128Mb: x32 SDRAM
Electrical Specifications – AC Operating Conditions
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime.
11. Auto precharge mode only.
12. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge states
(READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce
the data rate.
13. tCK = 7ns for -7, 6ns for -6/6A.
14. Address transitions average on transition every two clocks.
15. Timing is specified by tCKS. Clock(s) specified as a reference only at minimum cycle rate.
16. Timing is specified by tWR plus tRP. Clock(s) specified as a reference only at minimum cy-
cle rate.
17. Timing is specified by tWR.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2001 Micron Technology, Inc. All rights reserved.
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