MT48LC4M32B2B5-7 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC4M32B2B5-7' PDF : 79 Pages View PDF
128Mb: x32 SDRAM
Functional Description
Functional Description
In general, 128Mb SDRAM devices (1 Meg x 32 x 4 banks) are quad-bank DRAM that op-
erate at 3.3V and include a synchronous interface (all signals are registered on the posi-
tive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4096
rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE
command are used to select the bank and row to be accessed (BA[1:0] select the bank;
A[11:0] select the row). The address bits (A[7:0]) registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections pro-
vide detailed information covering device initialization, register definition, command
descriptions, and device operation.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
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© 2001 Micron Technology, Inc. All rights reserved.
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