MT55L512L18PF-7.5IT View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT55L512L18PF-7.5IT' PDF : 30 Pages View PDF
3.3V I/O AC TEST CONDITIONS
Input pulse levels ................................... VSS to 3.3V
Input rise and fall times ..................................... 1ns
Input timing reference levels .......................... 1.5V
Output reference levels ................................... 1.5V
Output load ............................. See Figures 1 and 2
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
2.5V I/O AC TEST CONDITIONS
Input pulse levels ................................... VSS to 2.5V
Input rise and fall times ..................................... 1ns
Input timing reference levels ........................ 1.25V
Output reference levels ................................. 1.25V
Output load ............................. See Figures 3 and 4
3.3V I/O Output Load Equivalents
Q
ZO= 50
50
VT = 1.5V
Figure 1
Q
351
+3.3V
317
5pF
Figure 2
2.5V I/O Output Load Equivalents
Q
ZO= 50Ω
50Ω
VT = 1.25V
Figure 3
Q
225Ω
+2.5V
225Ω
5pF
Figure 4
LOAD DERATING CURVES
The Micron 512K x 18, 256K x 32, and 256K x 36 ZBT
SRAM timing is dependent upon the capacitive loading
on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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