NT5CC64M16DP-BE View Datasheet(PDF) - Nanya Technology
Part Name
Description
MFG CO.
'NT5CC64M16DP-BE' PDF : 138 Pages View PDF
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Timing Parameters
In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, tAOF min/max.
Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance
begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are
measured from ODTLon.
Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off the ODT resistance. Maximum
RTT turn off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are
measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with
ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write command. ODTH4 and
ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until
ODT is registered low.
Fig. 48: Synchronous ODT Timing Example for AL=3; CWL=5; ODTLon=AL+CWL-2=6;
ODTLoff=AL+CWL-2=6
T0
CK
CK
CKE
ODT
DRAM_RTT
T1
T2
T3
T4
T5
AL=3
ODTH4, min
ODTLon = CWL + AL -2
T6
T7
T8
tAONmin
tAONmax
T9
T10
T11
T12
T13
T14
T15
AL=3
ODTLoff = CWL + AL -2
RTT_NOM
CWL - 2
tAONmax
tAONmin
Fig. 49: Synchronous ODT example with BL=4, WL=7
T0
CK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CK
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRS4
NOP
NOP
NOP
NOP
NOP
ODTH4
ODTH4
ODT
tAONmin
ODTH4min
ODTLoff = CWL -2
tAONmax
tAOFmax
tAOFmin
tAONmax
tAONmin
DRAM_RTT
ODTLon = CWL -2
RTT_NOM
ODTLon = CWL -2
Transitioning
Do not care
T13
T14
T15
T16
T17
T18
NOP
NOP
NOP
NOP
NOP
NOP
ODTLoff = WL - 2
tAOFmax
tAOFmin
Transitioning
Do not care
ODT must be held for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL=4) or ODTH8
(BL=8) after Write command (T7). ODTH is measured from ODT first registered high to ODT first registered
low, or from registration of Write command with ODT high to ODT registered low. Note that although ODTH4 is
satisfied from ODT registered at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from
the registration of the Write command at T7.
REV 1.2
May. 2011
CONSUMER DRAM
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All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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