NT5CC64M16DP-BE View Datasheet(PDF) - Nanya Technology
Part Name
Description
MFG CO.
'NT5CC64M16DP-BE' PDF : 138 Pages View PDF
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF)
after the write command, termination strength RTT_Nom is selected.
Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.
The following table shows latencies and timing parameters which are relevant for the on-die termination control in Dynamic
ODT mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set RTT_WR, MR2[A10,A9
= [0,0], to disable Dynamic ODT externally.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with
ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the Write command. ODTH4 and
ODTH8 are measured from ODT registered high to ODT registered low or from the registration of Write command until ODT
is register low.
Table 22: Latencies and timing parameters relevant for Dynamic ODT
Name and
Description
ODT turn-on
Latency
ODT turn-off
Latency
ODT Latency for
changing from
RTT_Nom to
RTT_WR
ODT Latency for
change from
RTT_WR to
RTT_Nom (BL=4)
ODT Latency for
change from
RTT_WR to
RTT_Nom (BL=8)
Minimum ODT high
time
after ODT assertion
Minimum ODT high
time
after Write (BL=4)
Minimum ODT high
time
after Write (BL=8)
RTT change skew
Abbr.
ODTLon
ODTLoff
ODTLcnw
ODTLcwn4
ODTLcwn8
ODTH4
ODTH4
ODTH8
tADC
Defined from
registering external
ODT signal high
registering external
ODT signal low
registering external
write command
registering external
write command
registering external
write command
registering ODT high
registering write with
ODT high
registering write with
ODT high
ODTLcnw
ODTLcwn
Defined to
turning
termination on
turning
termination off
change RTT
strength from
RTT_Nom to
RTT_WR
change RTT
strength from
RTT_WR to
RTT_Nom
change RTT
strength from
RTT_WR to
RTT_Nom
ODT registered
low
ODT registered
low
ODT register low
RTT valid
Definition for all DDR3/L
speed pin
ODTLon=WL-2
ODTLoff=WL-2
ODTLcnw=WL-2
ODTLcwn4=4+ODTLoff
ODTLcwn8=6+ODTLoff
ODTH4=4
ODTH4=4
ODTH8=6
tADC(min)=0.3tCK(avg)
tADC(max)=0.7tCK(avg)
Unit
tCK
tCK
tCK
tCK
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Note: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn)
REV 1.2
May. 2011
CONSUMER DRAM
© NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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