Power Integrated Processor for Digital Amplifier
NTP3000
PROTECT signal is changed to high by the FAULT signal after Hold Time and at the same time it
increases Auto PROTECT restore counter value by 1.
If the counter value reaches AVRCT (Auto PROTECT Restore Counter Threshold) in Auto PROTECT
restore interval, the PROTECT signal becomes low permanently. Designers can detect this permanent
low state by reading PPM flag in register Address 0x75 and change the permanent low state to high by
setting Auto PROTECT restore counter value to 0 by using FPMLD flag in register Address 0x1E. Also,
designers can control the PROTECT signal directly by using PWMM flag in register Address 0x1E.
Auto PROTECT restore interval is defined by PHT, AVRCT, IRC flags in register Address 0x1D and the
default value is PHT * AVRCT * IRC = 4 * 5 * 2 = 40msec.
6. Audio Input
6.1. I2S and Serial Audio Interface
Serial audio port of NTP3000 can be configured as either the master or slave mode, and BCK(bit clock)
and WCK(word clock) are bi-directional pins depending on the clock mode setting. In the master mode,
WCK(fs) and BCK(configurable) are output signals from the NTP3000, and the external DSP receiver
delivers SDATA signal synchronized with them. NTP3000 accepts WCK and BCK signal along with
SDATA coming from external devices in the slave mode. INS flag determines clock mode between
master and slave mode.
1/fs
WCK
(output)
1/64fs
L channel
R channel
BCK
(output)
SDATA
(input)
X L23 L22 L21 L20 L19 L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 X X X X X X X X L23 L22 L21 L20 L19 L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 X X X X X X X
MSB
LSB
MSB
LSB
* WCK and BCK are output when master mode, and input when slave mode.
Figure 10 Serial audio interface format
For general serial mode other than I2S, the format of data can be changed by LRJ(Left, Right Justify),
MLF(MSB, LSB First)and BS(Bit Size) flags of register Address 0x01. Figure 11 shows some examples
of general serial audio formats and their register settings.
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
10
R0.73-11.2006