NTP3000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'NTP3000' PDF : 37 Pages View PDF
Power Integrated Processor for Digital Amplifier
NTP3000
GEQ of CH2
(GEQC flags of 0x06
register = 0b11 &
0x3F = 0x08 case)
3D filter
(0x3F = 0x10 case)
Various1
(0x3F = 0x20 case)
Various2
(0x3F = 0x40 case)
BQ1
BQ1 of CH1
BQ of ALC
BQ1 of Ch3
Pre-biquad
BQ2
BQ3
BQ4
BQ2 of CH1 BQ1 of CH2 BQ2 of CH2
BQ1 of Ch1
Pre-biquad
BQ2 of Ch3
Pre-biquad
BQ2 of Ch1
Pre-biquad
BQ8 in Post-
Biquad
BQ1 of Ch2
Pre-biquad
BQ9 in Post-
Biquad
Table 2 Biquad filters
BQ5
X
BQ2 of Ch2
Pre-biquad
X
When the filter coefficients to download are same for, e.g. post biquad of ch1 and ch2 then set the
register 0x3F as 0x3.
There are 8 loudness gains in post-biquad chain. To download loudness gain of each biquad, page flag
register 0x3F should be set as in the case of downloading the filter coefficients.
loudness gains of CH1(0x3F = 0x01 case)
loudness gains of CH2(0x3F = 0x02 case)
loudness gains of CH3(0x3F = 0x80 case)
0x59
L11
L21
L31
Table 3 Loudness gain
0x5A
L12
L22
L32
0x5B
L13
L23
X
5. Clock, Reset & Control
5.1. System Clock
The internal system clock of NTP3000 is generated from external master clock by PLL. NTP3000
supports external master clock frequency from 8.192 MHz to 24.576MHz. For proper operation, PLL
should be set correctly according to master frequency (Table ).
5.2. Reset
When hardware RESET pin is set to low state, NTP3000 is brought into the reset state to bring up the
actions as follow.
1) Each control register resets to the default value.
2) All the internal registers, multipliers, adders, counters, and etc. are cleared to zero.
3) All of the output pins keep low state as long as the RESET is active.
It takes about 7µs after reset pin is remained low for more than 0.1usec to finish the above operations as
shown in Figure 7.
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
8
R0.73-11.2006
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