Power Integrated Processor for Digital Amplifier
1. BLOCK DIAGRAM
NTP3000
Figure 2 NTP3000 Block Diagram
2. PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28, 29
NAME
BST1A
VDR1A
/RESET
AD
VSS_IO
CLK_I
CLK_O
VDD_IO
DGNDPLL
AGNDPLL
LFM
AVDDPLL
DVDDPLL
VSS
DVSS
DVDD
SDATA2)
WCK2)
BCK2)
SDA2)
SCL2)
PWM_SWB
PWM_SWA
PROTECT
FAULT
VDR2B
BST2B
PGND2B
TYPE1)
P
P
I
I
-
I
O
P
-
-
I
P
P
-
-
P
I
I/O
I/O
I/O
I
O
O
O
I
P
P
-
DESCRIPTION
Bootstrap supply, external capacitor to OUT1A is required
Gate drive voltage regulator decoupling pin, capacitor to GND
Active Low to reset NTP3000, Schmitt trigger input
I2C device Address selection
Ground
System master clock input
System master clock output
voltage supply for I/O, 3.3V
Ground
Ground
External loop filter
voltage supply for PLL analog circuit, 1.8V
voltage supply for PLL digital circuit, 1.8V
Ground
Ground
voltage supply for core logic, 1.8V
I2S serial data input
I2S word clock
I2S bit clock
I2C data
I2C clock
PWM output for external subwoofer, negative
PWM output for external subwoofer, positive
External power stage on/off control to protect
input from external power stage
Gate drive voltage regulator decoupling pin, capacitor to GND
Bootstrap supply, external capacitor to OUT1A is required
Ground
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
3
R0.73-11.2006