128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
MODE
REGISTER
SET
MRS
REFS
REFSX
IDLE
REFA
AUTO
REFRESH
CKEL
CLK
SUSPEND
CKEH
ACT
CKEL
POWER
DOWN
CKEH
TERM
ROW
ACTIVE
TERM
WRITE
READ
WRITE
SUSPEND
CKEL
WRITE
CKEH
WRITEA READA
READ
WRITE
READ
CKEL READ
SUSPEND
CKEH
WRITEA
WRITEA READA
WRITEA
SUSPEND
CKEL
WRITEA
CKEH
PRE
PRE
PRE
READA
CKEL
READA
READA
SUSPEND
CKEH
POWER
APPLIED
POWER PRE
ON
PRE
CHARGE
Automatic Sequence
Command Sequence
JULY.2000
Page-14
Rev.2.2