P2V28S20ATP-7 View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'P2V28S20ATP-7' PDF : 51 Pages View PDF
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
WRITE
After tRCD from the bank activation, a WRITE command
can be issued. 1st input data is set at the same cycle as the
WRITE. Following (BL -1) data are written into the RAM,
when the Burst Length is BL. The start address is specified
by A0-A9(x4), A0-8(X8), A0-7(X16) and the address se-
quence of burst data is defined by the Burst Type. A WRITE
command may be applied to any active bank, so the row
precharge time (tRP) can be hidden behind continuous in-
put data by interleaving the multiple banks. From the last input
data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, the
autoprecharge (WRITEA) is performed. Any command (READ,
WRITE, PRE, TBST, ACT) to the same bank is inhibited till the
internal precharge is complete. The internal precharge begins at
tWR after the last input data cycle. (Need to keep tRAS min.) The
next ACT command can be issued after tRP from the internal
precharge timing.
WRITE with Auto-Precharge (BL=4)
CLK
Command
A0-9
A10
A11
BA0,1
DQ
CLK
Command
A0-9
A10
A11
BA0,1
DQ
ACT
Xa
tRCD
Write ACT
Y Xb
tRCD
Write PRE
Y
PRE
XXaa
0 Xb
0
0
0
XXaa
Xb
0
0
00
00 10
10 00
10
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Multi Bank Interleaving WRITE (BL=4)
ACT
Xa
Xa
Xa
00
tRCD
Write
Y
1
00
tWR
Da0 Da1 Da2 Da3
ACT
tRP
Xa
Xa
Xa
00
Internal precharge starts
JULY.2000
Page-19
Rev.2.2
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