128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
CLK
Command
Read
Address
Y
DQ
Q0 Q1 Q2 Q3
Write
Y
D0 D1 D2 D3
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Type
Burst Length
Initial Address BL
Column Addressing
A2 A1 A0
Sequential
Interleaved
00 0
012 345670123 4567
00 1
123 456701032 5476
01 0
234 567012301 6745
01 1
345 670123210 7654
8
10 0
456 701234567 0123
10 1
567 012345476 1032
11 0
670 123456745 2301
11 1
701 23456 7654 3210
- 00
012 3
0123
- 01
123 0
4
- 10
230 1
1032
2301
- 11
30 12
32 1 0
-- 0
01
2
-- 1
10
01
10
JULY.2000
Page-16
Rev.2.2