128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Power-Up Sequesce and Intialize
CLK
/CS
/RAS
200µs
tRP
tRFC
tRFC
tRSC
/CAS
/WE
CKE
DQM
A0-8
MA
X
A10
0
X
A9,11
0
X
BA0,1
0
0
DQ
NOP
Power On
PRE ALL REFA
REFA
REFA
MRS ACT# 0
Minimum 8 REFA cycles
Italic parameter indicates minimum case
JULY.2000
Page-45
Rev.2.2