PC8260 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'PC8260' PDF : 53 Pages View PDF
Table 4. External Signals (Continued)
Pin
Signal Name
TRIS
Three State
PORESET
Power-on Reset
HRESET
Hard Reset
SRESET
Soft Reset
QREQ
Quiescent Request
RSTCONF
Reset Configuration
MODCK1
AP[1]
TC[0]
BNKSEL[0]
MODCK2
AP[2]
TC[1]
BNKSEL[1]
Clock Mode Input
Address Parity 1
Transfer Code 0
Bank Select 0
Clock Mode Input
Address Parity 2
Transfer Code 1
Bank Select 1
PC8260 PowerQUICC II
Type
I
I
I/O
I/O
O
I
I
I/O
O
O
I
I/O
O
O
Description
Asserting TRIS forces all other PowerQUICC II’s pins to high impedance
state.
When asserted, this input line causes the PowerQUICC II to enter
power-on reset state.
This open drain line, when asserted, causes the PowerQUICC II to enter
hard reset state.
This open drain line, when asserted, causes the PowerQUICC II to enter
soft reset state.
This pin indicates that PowerQUICC II’s internal core is about to enter its
low power mode. In the PowerQUICC II, this pin will be typically used for
debug purposes.
This input lien is sampled by the PowerQUICC II during the assertion of
the HRESET signal. If the line is asserted, the configuration mode is
sampled in the form of the hard reset configuration word driven on the
data bus. When this line is negated, the default configuration mode is
adopted by the PowerQUICC II. Notice that the initial base address of
internal registers is determined in this sequence.
Defines the operating mode of internal clock circuits.
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on the address parity 1 pin should
provide odd parity (odd number of 1’s) on the group of signals that
includes address parity 1 and [A8:15].
The transfer code output pins supply information that can be useful for
debug purposes for each of the PowerQUICC II initiated bus
transactions.
The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x compatible bus mode.
Defines the operating mode of internal clock circuits.
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on the address parity 2 pin should
provide odd parity (odd number of 1’s) on the group of signals that
includes address parity 2 and [A16:23].
The transfer code output pins supply information that can be useful for
debug purposes for each of the PowerQUICC II initiated bus
transactions.
The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x compatible bus mode.
31
2131B–HIREL–02/03
Share Link: 
