PC8260 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'PC8260' PDF : 53 Pages View PDF
Table 4. External Signals (Continued)
Pin
Signal Name
MODCK3
AP[3]
TC[2]
BNKSEL[2]
Clock Mode Input
Address Parity 3
Transfer Code 2
XFC
CLKIN
PA[0:31]
PB[4:31]
PC[0:31]
PD[4:31]
VDD
VDDH
VCCSYN
GNDSYN
VCCSYN1
Bank Select 2
External Filter Capacitance
Clock In
Port A Bits 0:31
Port B Bits 4:31
Port C Bits 0:31
Port D Bits 4:31
Power Supply
Power Supply
Power Supply
Special Ground
Power Supply
Type
I
I/O
O
O
I
I
I/O
I/O
I/O
I/O
Description
Defines the operating mode of internal clock circuits.
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on the address parity 3 pin should
provide odd parity (odd number of 1’s) on the group of signals that
includes address parity 3and [A24:314].
The transfer code output pins supply information that can be useful for
debug purposes for each of the PowerQUICC II initiated bus
transactions.
The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x compatible bus mode.
Input connection for an external capacitor filter for PLL circuity.
Primary clock input to PowerQUICC II’s PLL.
General Purpose I/O Port
General Purpose I/O Port
General Purpose I/O Port
General Purpose I/O Port
Power supply of the internal logic
Power supply of the I/O buffers
Power supply of the PLL circuity
Special ground of the PLL circuity
Power supply of the core’s PLL circuity
32 PC8260 PowerQUICC II
2131B–HIREL–02/03
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