PCF2129T View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF2129T' PDF : 73 Pages View PDF
NXP Semiconductors
PCF2129T
Accurate RTC with integrated quartz crystal for industrial
Table 33. Programmable watchdog timer
TF[1:0] Timer source
Units Minimum timer
clock frequency
period (n = 1)
00
4.096
kHz 244
01
64
Hz 15.625
10
1
Hz 1
11
1⁄60
Hz 60
Units
s
ms
s
s
Maximum timer
period (n = 255)
62.256
3.984
255
15 300
Units
ms
s
s
s
8.10.3 Watchdog timer function
The watchdog timer function is enabled or disabled by the WD_CD bit of the register
Watchdg_tim_ctl (see Table 31).
The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock
frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz (see Table 33).
When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val
determines the watchdog timer period (see Table 33).
The watchdog timer counts down from the software programmed 8-bit binary value n in
register Watchdg_tim_val. When the counter reaches 1, the watchdog timer flag WDTF
(register Control_2) is set logic 1 and an interrupt will be generated.
The counter does not automatically reload.
When WD_CD is logic 0 (watchdog timer disabled) and the microcontroller unit (MCU)
loads a watchdog timer value n, then:
• the flag WDTF is reset
• INT is cleared
• the watchdog timer starts again
Loading the counter with 0 will:
• reset the flag WDTF
• clear INT
• stop the watchdog timer
Remark: WDTF is read only and cannot be cleared by command. WDTF can be cleared
by:
• loading a value in register Watchdg_tim_val
• reading of the register Control_2
Writing a logic 0 or logic 1 to WDTF has no effect.
PCF2129T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 February 2013
© NXP B.V. 2013. All rights reserved.
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