PCF8562TT/2 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8562TT/2' PDF : 36 Pages View PDF
NXP Semiconductors
PCF8562
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
Table 18. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Clock
fclk(int)
internal clock frequency
fclk(ext)
external clock frequency
tclk(H)
HIGH-level clock time
tclk(L)
LOW-level clock time
Synchronization
[1]
1 440
960
60
60
1 850
-
-
-
2 640
2 640
-
-
tPD(SYNC_N)
tSYNC_NL
tPD(drv)
I2C-bus[3]
SYNC propagation delay
SYNC LOW time
driver propagation delay
-
1
VLCD = 5 V
[2]
-
30
-
-
-
-
30
Pin SCL
fSCL
tLOW
tHIGH
Pin SDA
SCL clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
-
-
400
1.3
-
-
0.6
-
-
tSU;DAT
data set-up time
tHD;DAT
data hold time
Pins SCL and SDA
100
-
-
0
-
-
tBUF
bus free time between a STOP and
START condition
1.3
-
-
tSU;STO
tHD;STA
tSU;STA
set-up time for STOP condition
hold time (repeated) START condition
set-up time for a repeated START
condition
0.6
-
-
0.6
-
-
0.6
-
-
tr
rise time of both SDA and SCL signals fSCL = 400 kHz
-
-
0.3
fSCL < 125 kHz
-
-
1.0
tf
fall time of both SDA and SCL signals
-
-
0.3
Cb
capacitive load for each bus line
-
-
400
tw(spike)
spike pulse width
on the I2C-bus
-
-
50
Unit
Hz
Hz
s
s
ns
s
s
kHz
s
s
ns
ns
s
s
s
s
s
s
s
pF
ns
[1] Typical output duty factor: 50 % measured at the CLK output pin.
[2] Not tested in production.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
PCF8562
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 June 2011
© NXP B.V. 2011. All rights reserved.
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