PCF8566 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8566' PDF : 48 Pages View PDF
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
VLCD
VDD
R
≤
trise
2 Cbus
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
VSS
Fig 26. Cascaded PCF8566 configuration
VDD VLCD
5
12
SDA 1
SCL 2
17 to 40 24 segment drives
SYNC 3
PCF8566
CLK 4
OSC 6
13 to 16
7 8 9 10 11
A0 A1 A2 SA0 VSS
BP0 to BP3
(open-circuit)
LCD PANEL
(up to 1536
elements)
VDD
VLCD
SDA 1
SCL 2
SYNC 3
CLK 4
OSC 6
5
12
17 to 40
PCF8566
13 to 16
7 8 9 10 11
24 segment drives
4 backplanes
BP0 to BP3
A0 A1 A2 SA0 VSS
mgg384
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8566s. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex mode when PCF8566s with
differing SA0 levels are cascaded).
SYNC is organized as an input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor. A PCF8566 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF8566 to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF8566 are shown in Figure 27.
PCF8566_7
Product data sheet
Rev. 07 — 25 February 2009
© NXP B.V. 2009. All rights reserved.
34 of 48
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