Philips Semiconductors
(67 + 1) × 102 pixels matrix LCD driver
Product specification
PCF8813
15 DC CHARACTERISTICS
VDD1 = 1.7 to 3.3 V; VSS = 0 V; VLCD = 3.0 to 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX.
VDD1
supply voltage (logic circuits)
VDD2, VDD3 supply voltage (voltage multiplier)
note 1
1.7
−
3.3
2.4
−
4.5
VLCDIN
VLCDOUT
VLCD(tol)
LCD supply voltage input
generated LCD supply voltage
tolerance of generated LCD supply
voltage
note 2
note 3
3.0
−
9.0
4.5
−
9.0
−70
−
+70
IDD(tot)
total supply current
(IDD1 + IDD2 + IDD3)
normal mode; notes 4, 5, 6 −
Power-down mode; note 7 −
100
300
0.5
10
IDD1
supply current
ILCD
LCD supply current
external VLCD; notes 4, 6, 8 −
external VLCD; notes 4, 6, 8 −
10
35
30
−
Logic circuits
VOL
LOW-level output voltage
VOH
HIGH-level output voltage
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IL
leakage current
Column and row outputs
IOL = 0.5 mA
IOH = −0.5 mA
VI = VDD or VSS
VSS
−
0.8VDD −
VSS
−
0.8VDD −
−1
−
0.2VDD
VDD
0.2VDD
VDD
+1
Rcol
column output resistance
C0 to C101
Rrow
Vcol(tol)
Vrow(tol)
row output resistance R0 to R67
bias tolerance C0 to C101
bias tolerance R0 to R67
LCD supply voltage generator
VLCD = 7.6 V; note 9
VLCD = 7.6 V; note 9
note 9
note 9
−
5
−
5
−100 0
−100 0
20
20
+100
+100
TC
VLCD temperature compensation
VLCD(nom) = 8.6 V
temperature coefficient 0
temperature coefficient 1
temperature coefficient 2
temperature coefficient 3
−
0.00 −
−
−0.23 −
−
−0.48 −
−
−0.64 −
UNIT
V
V
V
V
mV
µA
µA
µA
µA
V
V
V
V
µA
kΩ
kΩ
mV
mV
mV/K
mV/K
mV/K
mV/K
Notes
1. VDD2 and VDD3 are always equal.
2. The maximum possible VLCD voltage that may be generated depends on voltage, temperature and load (display).
3. Valid for the temperature, VPR and TC values used at calibration.
4. Normal mode and internal clock.
5. Conditions: VDD1 = 1.8 V; VDD2 = 2.70 V; VLCD = 7.6 V; voltage multiplier = 4 × VDD2; bias system 1/9; inputs at VDD1
or VSS; VLCD generation = internal; VLCD output loaded by 10 µA; Tamb = 25 °C.
6. fINTCLK = 0 (no data bus clock).
7. Power-down mode; during Power-down all static currents are switched off.
2004 Mar 05
39