Philips Semiconductors
(67 + 1) Γ 102 pixels matrix LCD driver
Product speciο¬cation
PCF8813
8. VLCD external voltage applied to VLCDIN and VLCDSENSE inputs; VLCDOUT disconnected; VPR and PC set to 0 (charge
pump off); display load current is not transmitted to IDD.
9. Load current = 10 Β΅A; outputs tested one at a time.
16 AC CHARACTERISTICS
VDD1 = 1.7 to 3.3 V; VSS = 0 V; VLCD = 3.0 to 9.0 V; Tamb = β40 to +85 Β°C; all timings speciο¬ed are based on
20% to 80% of VDD with an input voltage swing of VSS to VDD; unless otherwise speciο¬ed.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX.
fext
fframe
tVHRL
tRW
tR(oper)
external clock frequency
frame frequency
VDD on to RES LOW time
reset pulse width LOW time
end of reset pulse to interface
operational
note 1
internal oscillator
note 2
note 3
see Fig.37
see Fig.37
see Fig.37
20
38
65
56
66
76
62
69
76
0(4)
β
1
500
β
β
1000 β
β
6800-type parallel bus; VDD1 = 1.8 to 3.3 V; see Figs 38 and 39
tDCSU
tDCHD
TDS(cyc)
tDSL
tDSH
tRWSU
tRWHD
tESU
tEHD
tDATSU
tDATHD
tDATACC
tDATOH
data/command set-up time
data/command hold time
data strobe cycle time
data strobe LOW time
data strobe HIGH time
read/write set-up time
read/write hold time
chip enable set-up time
chip enable hold time
data set-up time
data hold time
output access time
output disable time
8080-type parallel bus; VDD1 = 1.8 to 3.3 V; see Fig.40
tDCSU
tDCHD
data/command set-up time
data/command hold time
TDS(cyc)
tDSLR
tDSLW
data strobe cycle time
data strobe LOW time (read)
data strobe LOW time (write)
tDSHR
tDSHW
tDATSU
data strobe HIGH time (read)
data strobe HIGH time (write)
data set-up time
tDATHD
tDATACC
tDATOH
data hold time
output access time
output disable time
0
β
25
0
β
β
1000 β
β
300
β
β
300
β
β
0
β
β
0
β
β
0
β
β
0
β
β
80
β
β
30
β
β
β
β
280
10
β
200
0
β
25
0
β
β
1000 β
β
120
β
β
240
β
β
120
β
β
120
β
β
80
β
β
30
β
β
β
β
280
10
β
200
UNIT
kHz
Hz
Hz
Β΅s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2004 Mar 05
40