PDSP16112/A View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
'PDSP16112/A' PDF : 18 Pages View PDF
Switching Characteristics
PDSP16116/A/MC
Characteristic
PDSP16116 PDSP16116A
Units
Min. Max. Min. Max.
Conditions
CLK rising edge to P-PORTS
CLK rising edge to WTOUT1:0
CLK rising edge to GWR4:0
CLK rising edge to SFTA1:0
CLK rising edge to SFTR2:0
Setup CEX or CEY to CLK rising edge
Hold CEX or CEY to CLK rising edge
Setup X or Y port inputs to CLK rising edge
Hold X or Y port inputs to CLK rising edge
Setup WTA1:0, WTB1:0, SOBFP or EOPSS inputs
to CLK rising edge
5
45 5
5
30 5
5
30 5
5
60 5
5
50 5
11
-
8
-
0
-
11
-
8
-
2
-
14
-
8
23 ns 2 x LSTTL + 20pF
20 ns 2 x LSTTL + 20pF
20 ns 2 x LSTTL + 20pF
30 ns 2 x LSTTL + 20pF
28 ns 2 x LSTTL + 20pF
- ns
0 ns
- ns
0 ns
- ns
Hold WTA1:0, WTB1:0, SOBFP or EOPSS inputs to
-
CLK rising edge
0
-
0 ns
Setup CONX or CONY inputs to CLK rising edge
Hold CONX or CONY inputs to CLK rising edge
Setup AR15:13 or AI15:13 to CLK rising edge
Hold AR15:13 or AI15:13 to CLK rising edge
OPSEL to valid P-PORTS
OER or OEI rising PR-PORT or PI-PORT high to Z
OER or OEI rising PR-PORT or PI-PORT low to Z
OER or OEI falling PR-PORT or PI-PORT Z to high
OER or OEI falling PR-PORT or PI-PORT Z to low
Clock period
Clock high time
Clock low time
Vcc Current (CMOS input levels)
Vcc Current (TTL input levels)
14
-
8
- ns
-
0
-
0 ns
14
-
-
- ns
-
0
-
0 ns
-
35 -
20 ns 2 x LSTTL + 20pF
-
35 -
25 ns see Fig.9
-
45 -
25 ns see Fig.9
-
22 -
18 ns see Fig.9
-
24 -
18 ns see Fig.9
100 -
50
- ns
30
-
12
- ns
20
-
12
- ns
-
60 -
80 mA see Note 4
- 100 - 130 mA see Note 4
NOTE 4 :- V = Max Outputs unloaded, clock freq = Max
CC
Test
Waveform - measurement level
Delay from output
VH
high to output
high impedance
0.5V
Delay from output
low to output
high impedance
VL
0.5V
V T = 0V
V T = Vcc
VT
1.5K Ω
DUT
30pF
Fig.10 Three state delay measurement load
Delay from output
high impedance to
output low
1.5V
0.5V
Delay from output
high impedance to
output high
1.5V
0.5V
VH - Voltage reached wh en output driven hig
VL - Voltage reached wh en output driven low
17
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