PDSP16488A/C0/AC View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
'PDSP16488A/C0/AC' PDF : 33 Pages View PDF
BIT 7
This bit controls the bypass option on the first line
delay on the L7:0 inputs. It is only effective when an
8 bit pixel mode is selected, which also needs more
than four line delays. When L7:0 are used as outputs
it should always be reset. In the 16-bit modes the
bypass function is only controlled by the BYPASS pin,
and the bit is redundant.
Bit Code
Function
0
0
Second line delay group fed from the
first group
0
1
Second line delay group fed from L7:0
which become inputs
2:1
00 Store pixels to end of line
2:1
01 Store pixels till count is reached
2:1
10 Frame store operation
2:1
11 Not Used
3
0
No delays on pixel inputs
3
1
4 delays on both pixel inputs
4
0
Use expansion adder
4
1
Expansion adder disabled
6:5
Not used
7
0
Use first delay in second group
7
1
Bypass first delay in second group
Table 9 Register B bit functions
Register C bit allocation (Table 10)
BIT 0 If this bit is set, the 20-bit field selected from the 32-bit
result, is defined automatically by internal logic.
BITS 3:1
These bits are in conjunction with register D, bits 7:5
to define the pixel delay from the HRES input to the
DELOP output. They are used to match the appropri-
ate processing delay in a particular system. The
minimum delay is 29 pixel clocks.
BITS 5:4 These bits define which of the four 20-bit fields out of
the 32-bit final result is selected as the input to the gain
control. They are redundant when the gain control is
not used, or if register C, bit 0, is set.
BITS 7:6
These bits define the use of the gain control as given
in Table 10. Intermediate devices in a multiple device
system must bypass the gain control block, otherwise
the additional pipeline delays will affect the result.
Disabling the gain control block will reduce the device
pipeline by 13 CLK cycles from the delays shown in
Table 6.
Bit Code
Function
0
0 Field selection defined by C5:4
0
1 Automatic field selection
3:1
000 DELOP = 2910 clocks
3:1
001 DELOP = 2918 clocks
3:1
010 DELOP = 29116 clocks
Table 10 Register C bit functions (continues…)
Bit Code
PDSP16488A
Function
3:1
011 DELOP = 29124 clocks
3:1
100 DELOP = 29132 clocks
3:1
101 DELOP = 29140 clocks
3:1
110 DELOP = 29148 clocks
3:1
111 DELOP = 29156 clocks
5:4
00 Select upper 20 bits
5:4
01 Select next 20 bits
5:4
10 Select next 20 bits
5:4
11 Select bottom 20 bits
7:6
00 By-pass the gain control
7:6
01 Normal gain control output
7:6
10 Saturate at max.1ve and 2ve values.
7:6
11 Force 2ve to zero.Sat.1ve values.
Table 10 Register C bit functions (continued)
Register D bit allocation (Table 11)
BIT 0 If this bit is set the expansion data input is delayed
by four pixel clocks before it is added to the present
convolver output. It is used in multiple device systems
when the partial window width is 8 pixels.
BIT 1
When this bit is set the internal sum is shifted to the
left by 8 places before being added to the expansion
input. It is used when two devices are used, each in an
8-bit pixel mode, to construct a 16-bit pixel mode.
BITS 3:2 These bits define the delays on both sets of pixel
inputs before entering the line stores. The delays are
always identical on both sets.
BIT 4
When this bit is set the convolver interprets 8 or 16-
bit pixels as 2’s complement signed numbers
BIT 7:5 These bits add 0 to 7 additional clock delays to those
selected by Register C, bits 3:1.
Bit Code
Function
0
0 X15:0 Not delayed
0
1 X15:0 Delayed
1
0 Internal sum not shifted
1
1 Internal sum multiplied by 256
3:2
00 Input to line stores not delayed
3:2
01 Input to line stores delayed by 4
3:2
10 Input to line stores delayed by 8
3:2
11 Input to line stores delayed by 12
4
0 Unsigned pixel data input
4
1 2’s complement pixel data input
7:5 XXX Add 0 to 7 clock delays to DELOP
Table 11 Register D bit functions
15
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