PDSP16488A/C0/AC View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
'PDSP16488A/C0/AC' PDF : 33 Pages View PDF
PDSP16488A
Switching Characteristics for Host mode
Characteristic
Symbol
Value
Units
Min. Max.
Conditions
DS hold time after R E P LY low
tDSH
20
ns Only applicable for Read ops and if REPLY is used
Host address/data setup time
tHSU
0
ns Only applicable if REPLY is used (Note 1)
Read setup time to prevent Write
tRA
5
ns
Host signal hold time
tHH
10
ns Must always be guaranteed
Expansion in to data out in PROG mode tDEL
30 ns No clocks are needed in PROG mode
Delay from DS low to PC1 low (Note 2) tEXP
50 ns Greater than tDEL under all conditions
CE setup time
tCSU
0
ns
CE hold time
tCH
0
ns
PROG setup time
tPSU
0
ns
PROG hold time
tPH
0
ns
PC1 high delay after DS high
tPCH
50 ns Defines DS high time
Coefficient read time
tACC
50 ns From Master or Single device
Coefficients valid time before REPLY
tRSU
5
ns
NOTES
1. If REPLY is not used, time is referenced to the rising edge of DS and when set up must be N3tDEL for N devices.
2. Equivalent to PC0 to PC1 delay
DS
CE
PROG
COEFFICIENT OUTPUT, X7:0
PC1 FROM MASTER OR SINGLE DEVICE
PC1 FROM LAST DEVICE (REPLY)
R/W FROM HOST
ADDRESS/DATA FROM HOST
HOST DATA OUTPUT FROM FIRST DEVICE
DATUM
tWAIT > tPCH
tCSU
tCH
tPSU
tPH
tACC
tEXP
tRSU
tPCH
tDSH
tRA
tHSU
tHH
VALID
tDEL
VALID
Fig. 10 Host timing
18
Share Link: 
