PF38F1602CT70 View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'PF38F1602CT70' PDF : 75 Pages View PDF
C3 SCSP Flash Memory
Table 28.
Offset(1)
P = 35h
(P+9)h
(P+A)h
(P+B)h
(P+C)h
(P+D)h
Primary-Vendor Specific Extended Query (Sheet 2 of 2)
Length
1
2
1
1
Description
(Optional Flash Features and Commands)
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Page mode read supported
bit 8 Synchronous read supported
Supported functions after suspend: read array, status, query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
VCC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
Addr.
Hex
Code
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 0
bit 8 = 0
Value
No
Yes
Yes
No
No
3E:
--01
bit 0 = 1
Yes
3F:
--03
40:
--00
bit 0 = 1
Yes
bit 1 = 1
Yes
41:
--33
3.3 V
42:
--C0 12.0 V
Table 29. Protection Register Information
Offset(1)
P = 35h
Length
Description
(Optional Flash Features and Commands)
(P+E)h
1
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
(P+F)h
Protection Field 1: Protection Description
(P+10)h
(P+11)h
This field describes user-available One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device-
unique serial numbers. Others are user programmable. Bits 0–15 point
to the Protection register Lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-programmable.
4
bits 0–7 = Lock/bytes JEDEC-plane physical low address
bits 8–15 = Lock/bytes JEDEC -plane physical high address
bits 16–23 = “n” such that 2n = factory pre- programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
(P+12)h
(P+13)h
Reserved for future use
Note: 1. The variable P is a pointer which is defined at CFI offset 15h.
Addr.
43:
44:
45:
46:
47:
48:
Hex
Code
--01
--80
--00
--03
--03
Value
01
80h
00h
8 byte
8 byte
26 Aug 2005
58
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
Datasheet
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