PI6CV857LA View Datasheet(PDF) - Pericom Semiconductor
Part Name
Description
MFG CO.
'PI6CV857LA' PDF : 9 Pages View PDF
PI6CV857L
PLL Clock Driver for
2.5V DDR-SDRAM Memory 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Pinout Table
Pin Name
Pin No.
I/O Type
Description
CLK
13
CLK
14
I Reference Clock input
Yx 3,5,10,20,22,27,29,39,44,46
Clock outputs.
Yx
FBOUT
FBOUT
2,6,9,19,23,26,30,40,43,47
32
33
O Complement Clock outputs.
Feedback output, and Complement Feedback Output
FBIN
36
FBIN
35
Feedback output, and Complement Feedback Output
PWRDWN
37
I
Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0,
the part is powered down and the differential clock outputs are disabled to a
3-state. When PWRDWN = 1, all differential clock outputs are enabled and run
at the same frequency as CLK.
VDDQ
AVDD
4,11,12,15,21,28,34,38,45
16
Power
Power Supply for I/O.
Analog /core power supply. AVDD can be used to bypass the PLL for testing
purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is
buffered directly to the device outputs.
AGND
GND
17
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground
1,7,8,18,24,25,31,41,42,48
Ground
Function Table
Inputs
Outputs
PLL State
AVDD
G
CLK
CLK
Y
GND
H
L
H
L
Y
FBOUT
FBOUT
H
L
H
Bypassed/off
GND
H
H
L
H
L
H
L
Bypassed/off
X
L
L
H
Z
Z
Z
Z
off
X
L
H
L
Z
Z
Z
Z
off
2.5V(nom)
H
L
H
L
H
L
H
on
2.5V(nom)
H
H
L
H
L
H
L
on
2.5V(nom)
X
<20 MHz (1)
Z
Z
Z
Z
off
Notes: For testing and power saving purposes, PI6CV857L will power down if the frequency of the reference inputs CLK, CLK is well
below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CV857L will be
powered down when the CLK,CLK stop running.
Z = High impedance
X = Dont care
2
PS8543 06/11/01
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