PI6CV857L
PLL Clock Driver for
2.5V DDR-SDRAM Memory 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
DC Specifications
Recommended Operating Conditions
Symbol
Parameter
AVDD Analog/core supply voltage
VDDQ Output supply voltage
VIL Low-level input voltage for PWRDWN pin
VIH High-level input voltage for PWRDWN pin
VOH High-level output voltage
VOL Low-level output voltage
VIX Input differential-pair crossing voltage
VOX Output differential-pair crossing voltage at the DRAM clock input
VIN Input voltage level
VID Input differential voltage between CK and CK
VOD Output differential voltage between Y[n] &Y[n] and FBOUT & FBOUT
TA Operating free air temperature
Min.
2.3
2.3
0.3
1.7
1.8
0
(VDDQ/2) 0.2
(VDDQ/2) 0.2
0.3
0.36
0.7
0
Nom.
2.5
2.5
Max.
Units
2.7
2.7
0.7
VDDQ +0.3
VDDQ
0.5
V
(VDDQ/2) +0.2
(VDDQ/2) +0.2
VDDQ +0.3
VDDQ +0.6
VDDQ +0.6
70
°C
Electrical Characteristics
Parameter
Test Conditions
VIK All inputs
II = 18mA
II
CK, FBIN
PWRDWN
VI = VDDQ or GND
VI = VDDQ or GND
IDDQ
Dynamic supply current of VDDQ
Static supply current
VDD = 2.7V
CK & CK <20 MHz or
PWRDWN = Low (1)
IADD
Dynamic supply current of AVDD
Static supply current
VDD = 2.7V
CK & CK <20 MHz or
PWRDWN = Low (1)
CK and CK
CI
FBIN and FBIN
VI = VDD or GND
Note:
1. The maximum power-down clock frequency is below 20 MHz.
AVDD, VDDQ
2.3V
Min.
Typ. Max. Units
1.2 V
2.7V
±10 µA
300 mA
100 µA
12 mA
100 µA
2.5V
2.0
3.0 pF
4
PS8543 06/11/01