PI6CV857LA View Datasheet(PDF) - Pericom Semiconductor
Part Name
Description
MFG CO.
'PI6CV857LA' PDF : 9 Pages View PDF
PI6CV857L
PLL Clock Driver for
2.5V DDR-SDRAM Memory 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
AC Specifications
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 )
Parameter
Description
Diagram
AVCC, VDDQ = 2.5V ±0.2V
Min.
Nom.
Max
Units
tjit(cc)
Cycle-to-cycle jitter
see Figure 3
75
75
t(q)
Static phase offset(1)
see Figure 4
50
0
50
tsk(o)
Output clock skew
see Figure 5
100
ps
tjit(per)
Period jitter
see Figure 6
75
75
tjit(hper)
Half-period jitter
see Figure 7
100
100
tsl(i)
tsl(o)
Input clock slew rate(2)
Output clock slew rate(2)
see Figure 8
1.0
see Figure 8
1.0
2.0
V/ns
2.0
The PLL on the PI6CV857L is capable of meeting all the above parameters while supporting SSC synthesizers with the following
parameters(3).
SSC modulation frequency
30.00
50.00
kHz
SSC clock input frequency deviation
0.00
0.50
%
PLL loop bandwidth
2
MHz
Phase angle
0.031 degrees
Notes:
1. Static Phase offset does not include Jitter.
2. The slew rate is determined from the IBIS model with test load shown in Figure1.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
5
PS8543 06/11/01
Share Link: 
