PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
3.2.2 Secondary Bus Interface Signals
Name
Pin #
Type
S1_AD[31:0],
S2_AD[31:0]
B20, B19, C20, C19, PB
C18, D20, D19, D17,
E19, E18, E17, F20,
F19, F17, G20, G19,
L20, L19, L18, M20,
M19, M17, N20, N19,
N18, N17, P17, R20,
R19, R18, T20, T19
J4, H1, H2, H3, H4, G1,
G3, G4, F2, F3, F4, E1,
E4, D1, C1, B1, C5, B5,
D6, C6, B6, A6, C7, B7,
D8, C8, D9, C9, B9, A9,
D10, C10
S1_CBE[3:0], E20, G18, K17, P20
PB
S2_CBE[3:0] F1, A1, A4, A7
S1_PAR,
K18,
PB
S2_PAR
B4
S1_FRAME#, H20,
S2_FRAME# D2
S1_IRDY#,
S2_IRDY#
H19,
B2
S1_TRDY#,
S2_TRDY#
H18,
A2
S1_DEVSEL#, J20,
S2_DEVSEL# D3
PSTS
PSTS
PSTS
PSTS
Description
Secondary Address/Data. Multiplexed address and data bus.
Address is indicated by S1_FRAME# or S2_FRAME# assertion.
Write data is stable and valid when S1_IRDY# or S2_IRDY# is
asserted and read data is stable and valid when S1_TRDY# or
S2_TRDY# is asserted. Data is transferred on rising clock edges
when both S1_IRDY# and S1_TRDY# or S2_IRDY# and
S2_TRDY# are asserted. During bus idle, PI7C7100 drives
S1_AD or S2_AD to a valid logic level when the S1_GNT# or
S2_GNT# is asserted respectively.
Secondary Command/Byte Enables. Multiplexed command
field and byte enable field. During the address phase, the initiator
drives the transaction type on these pins. After that the initiator
drives the byte enables during data phases. During bus idle,
PI7C7100 drives S1_CBE[3:0] or S2_CBE[3:0] to a valid logic
level when the internal grant is asserted.
Secondary Parity. Parity is even across S1_AD[31:0],
S1_CBE[3:0], and S1_PAR or S2_AD[31:0], S2_CBE[3:0], and
S2_PAR (i.e. an even number of '1's). S1_PAR or S2_PAR is an
input and is valid and stable one cycle after the address phase
(indicated by assertion of S1_FRAME# or S2_FRAME#) for
address parity. For write data phases, S1_PAR or S2_PAR is an
input and is valid one clock after S1_IRDY# or S2_IRDY# is
asserted. For read data phase, S1_PAR or S2_PAR is an output
and is valid one clock after S1_TRDY# or S2_TRDY# is asserted.
Signal S1_PAR or S2_PAR is 3-stated one cycle after the S1_AD
or S2_AD lines are tri-stated. During bus idle, PI7C7100 drives
S1_PAR or S2_PAR to a valid logic level when the internal grant is
asserted.
Secondary FRAME (Active LOW). Driven by the initiator of a
transaction to indicate the beginning and duration of an access.
De-assertion of S1_FRAME# or S2_FRAME# indicates the final
data phase requested by initiator. Before being 3-stated, it is
driven to a de-asserted state for one cycle.
Secondary IRDY (Active LOW). Driven by the initiator of a
transaction to indicate its ability to complete the current data
phase on the primary side. Once asserted in a data phase, it is
not de-asserted until end of the data phase. Before being 3-stated,
it is driven to a de-asserted state for one cycle.
Secondary TRDY (Active LOW). Driven by the target of a
transaction to indicate its ability to complete the current data
phase on the primary side. Once asserted in a data phase, it is
not de-asserted until end of the data phase. Before being 3-stated,
it is driven to a de-asserted state for one cycle.
Secondary Device Select (Active LOW). Asserted by the target
indicating that the device is accepting the transaction. As a
master, PI7C7100 waits for the assertion of this signal within 5
cycles of S1_FRAME# or S2_FRAME# assertion; otherwise,
terminate with master abort. Before being 3-stated, it is driven to a
de-asserted state for one cycle.
6
09/18/00 Rev 1.1
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