PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
3.2.2 Secondary Bus Interface Signals (continued)
Name
Pin #
Type Description
S1_STOP#,
J19,
S2_STOP#
C3
PSTS
Secondary STOP (Active LOW). Asserted by the target indicating that the
target is requesting the initiator to stop the current transaction. Before being
3-stated, it is driven to a de-asserted state for one cycle.
S1_LOCK#,
J18,
S2_LOCK#
B3
S1_PERR#,
J17,
S2_PERR#
D4
PSTS
PSTS
S1_SERR#,
K20,
PI
S2_SERR#
C4
S1_REQ#[7:0], B11, A12, PIU
D13, C13,
C15, A16,
C17, B17
S2_REQ#[7:0] T2, R3, P2,
P1, M2, M1,
K1, K3
S1_GNT#[7:0], C11, B12, PO
B13, A14,
D14, B16,
D16, B18
S2_GNT#[7:0] U1, P4, R1,
N4, M3, L4,
L1, K2
S1_RESET#, B10,
PO
S2_RESET# T4
S1_EN,
W3,
PIU
S2_EN
W4
S_M66EN
D7
–
S_CFN#
Y2
CIU
Secondary LOCK (Active LOW). Asserted by master for multiple transactions
to complete.
Secondary Parity Error (Active LOW). Asserted when a data parity error is
detected for data received on the secondary interface. Before being 3-stated, it
is driven to a de-asserted state for one cycle.
Secondary System Error (Active LOW). Can be driven LOW by any device to
indicate a system error condition.
Secondary Request (Active LOW). This is asserted by an external device to
indicate that it wants to start a transaction on the Secondary bus. The input is
externally pulled up through a resistor to VDD.
Secondary Grant (Active LOW). PI7C7100 asserts this pin to access the
secondary bus. PI7C7100 de-asserts this pin for at least 2 PCI clock cycles
before asserting it again. During idle and S1_GNT# or S2_GNT# asserted,
PI7C7100 will drive S1_AD, S1_CBE and S1_PAR or S2_AD, S2_CBE and
S2_PAR to valid logic levels.
Secondary RESET (Active LOW). Asserted when any of the following
conditions are met:
1. Signal P_RESET# is asserted.
2. Secondary reset bit in bridge control register in configuration
space is set.
When asserted, all control signals are 3-stated and zeros are driven
on S1_AD, S1_CBE, and S1_PAR or S2_AD, S2_CBE, and S2_PAR.
Secondary Enable (Active HIGH). When S1_EN or S2_EN is inactive,
secondary PCI S1 or S2 bus will be asynchronously 3-stated.
Reserved for Future Use. Must be tied to ground.
Secondary Bus Central Function Control Pin. When tied LOW, it enables
the internal arbiter. When tied HIGH, an external arbiter must be used.
S1_REQ0# or S2_REQ0# is reconfigured to be the secondary bus grant input,
and S1_GNT0# or S2_GNT0# is reconfigured to be the secondary bus request
output.
7
09/18/00 Rev 1.1
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