PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
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MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
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4. PCI Bus Operation
This chapter offers information about PCI transactions, transaction forwarding across PI7C7100, and transaction
termination. The PI7C7100 has three 128-byte buffers for buffering of upstream and downstream transactions. These hold
addresses, data, commands, and byte enables and are used for both read and write transactions.
4.1 Types of Transactions
This section provides a summary of PCI transactions performed by PI7C7100. Table 4–1 lists the command code and
name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C7100
initiates transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when PI7C7100 responds to
transactions as a target, on the primary (P) and secondary (S1, S2) buses.
Table 4-1. PCI Transactions
Type of Transactions
Initiates as Master
Responds as Target
Primary
Secondary
Primary
Secondary
0000 Interrupt acknowledge
N
N
N
N
0001 Special cycle
Y
Y
N
N
0010 I/O read
Y
Y
Y
Y
0011 I/O write
Y
Y
Y
Y
0100 Reserved
N
N
N
N
0101 Reserved
N
N
N
N
0110 Memory read
Y
Y
Y
Y
0111 Memory write
Y
Y
Y
Y
1000 Reserved
N
N
N
N
1001 Reserved
N
N
N
N
1010 Configuration read
N
Y
Y
N
1011 Configuration write
Y (Type 1 only)
Y
Y
Y (Type 1 only)
1100 Memory read multiple
Y
Y
Y
Y
1101 Dual address cycle
N
N
N
N
1110 Memory read line
Y
Y
Y
Y
1111 Memory write and invalidate
N
N
Y
Y
As indicated in Table 4–1, the following PCI commands are not supported by PI7C7100:
• PI7C7100 never initiates a PCI transaction with a reserved command code and, as a target, PI7C7100 ignores
reserved command codes.
• PI7C7100 does not generate interrupt acknowledge transactions. PI7C7100 ignores interrupt acknowledge
transactions as a target.
• PI7C7100 does not respond to special cycle transactions. PI7C7100 cannot guarantee delivery of a special cycle
transaction to downstream buses because of the broadcast nature of the special cycle command and the inability
to control the transaction as a target. To generate special cycle transactions on other PCI buses, either upstream
or downstream, Type 1 configuration write must be used.
• PI7C7100 neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0
configuration transactions on the secondary PCI buses.
• PI7C7100 does not support DAC (Dual Address Cycle) transactions.
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09/18/00 Rev 1.1
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