PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
Table 4–6. Device Number to IDSEL S1_AD or S2_AD Pin Mapping
Device Number
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h-1Eh
1Fh
P_AD<15:11>
00000
00001
00010
00011
00100
00101
0110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000-11110
11111
Secondary IDSEL S1_AD[31:16]
or S2_AD[31:16]
0000 0000 0000 0001
0000 0000 0000 0010
0000 0000 0000 0100
0000 0000 0000 1000
0000 0000 0001 0000
0000 0000 0010 0000
0000 0000 0100 0000
0000 0000 1000 0000
0000 0001 0000 0000
0000 0010 0000 0000
0000 0100 0000 0000
0000 1000 0000 0000
0001 0000 0000 0000
0010 0000 0000 0000
0100 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
Generate special cycle (P_AD[7:2] = 00h)
0000 0000 0000 0000 (P_AD[7:2] = 00h)
S1_AD or S2_AD Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
-
PI7C7100 can assert up to 16 unique address lines to be used as IDSEL signals for up to 16 devices on the secondary
bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than
16 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method
of generating IDSEL lines must be used, and no upper address bits are then asserted. The configuration transaction is
still translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device,
the transaction ends in a master abort.
PI7C7100 forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0
configuration read or write transactions are limited to a single 32-bit data transfer.
4.7.3 Type 1 to Type 1 Forwarding
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-
to-PCI bridges are used.
When PI7C7100 detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus,
PI7C7100 forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type
0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to
Type 1 forwarding occurs when the following conditions are met during the address phase:
• The lowest two address bits are equal to 01b.
• The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the
upper limit (inclusive) in the subordinate bus number register.
• The bus command is a configuration read or write transaction.
21
09/18/00 Rev 1.1
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