PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
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MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
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4.6 Read Transactions
Delayed read forwarding is used for all read transactions crossing PI7C7100. Delayed read transactions are treated as
either prefetchable or non-prefetchable. Table 4-4 shows the read behavior, prefetchable or non-prefetchable, for each
type of read operation. For Timing diagrams, see Figures 11-14 and 23-26 in Appendix A
4.6.1 Prefetchable Read Transactions
A prefetchable read transaction is a read transaction where PI7C7100 performs speculative DWORD reads, transferring
data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist
of multiple data transfers. However, byte enable bits cannot be forwarded for all data phases as is done for the single data
phase of the non-prefetchable read transaction. For prefetchable read transactions, PI7C7100 forces all byte enable bits
to be turned on for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read
transactions that fall into prefetchable memory space.
The amount of data that is pre-fetched depends on the type of transaction. The amount of pre-fetching may also be affected
by the amount of free buffer space available in PI7C7100, and by any read address boundaries encountered.
Pre-fetching should not be used for those read transactions that have side effects in the target device, that is, control and
status registers, FIFOs, and so on. The target device’s base address register or registers indicate if a memory address region
is prefetchable.
4.6.2 Non-prefetchable Read Transactions
A non-prefetchable read transaction is a read transaction where PI7C7100 requests one and only one DWORD from the
target and disconnects the initiator after delivery of the first DWORD of read data. Unlike prefetchable read transactions,
PI7C7100 forwards the read byte enable information for the data phase.
Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for memory read transactions
that fall into non-prefetchable memory space.
If extra read transactions could have side effects, for example, when accessing a FIFO, use non-prefetchable read
transactions to those locations. Accordingly, if it is important to retain the value of the byte enable bits during the data phase,
use non-prefetchable read transactions. If these locations are mapped in memory space, use the memory read command and
map the target into non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior.
4.6.3 Read Pre-fetch Address Boundaries
PI7C7100 imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of
these aligned address boundaries, the PI7C7100 stops pre-fetched data, unless the target signals a target disconnect
before the read pre-fetched boundary is reached. When PI7C7100 finishes transferring this read data to the initiator, it
returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched
read data is delivered. Any leftover pre-fetched data is discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address boundary, or until the
initiator de-asserts FRAME#. Section 4.6.6 describes flow-through mode during read operations.
Table 4-5 shows the read pre-fetch address boundaries for read transactions during non-flow-through mode.
Type of Transaction
Config read
I/O read
Memory read
Memory read
Memory read
Memory read line
Memory read line
Memory read multiple
Memory read multiple
Table 4-4. Read Pre-fetch Address Boundaries
Address Space
Cache Line Size (CLS)
Pre-fetch Aligned Address Boundary
-
-
One DWORD (no pre-fetch)
-
-
One DWORD (no pre-fetch)
Non-prefetchable -
One DWORD (no pre-fetch)
Prefetchable
CLS not equal to 1, 2, 4, 8 16-DWORD aligned address boundary
Prefetchable
CLS = 1, 2, 4, 8
Cache line address boundary
-
CLS not equal to 1, 2, 4, 8 16-DWORD aligned address boundary
-
CLS = 1, 2, 4, 8
Cache line boundary
-
CLS not equal to 1, 2, 4, 8 32-DWORD aligned address boundary
-
CLS = 1, 2, 4, 8
2 times of cache line boundary
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09/18/00 Rev 1.1
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