ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
16. Electrical and Timing Specifications
16.1 Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested).
Storage Temperature
–65°C to +150°C
Ambient Temperature with Power applied
0°C to +70°C
Supply Voltage to Ground Potentials (Inputs & AVCC, VDD only)
–0.3V to +3.6V
DC Input Voltage
–0.5V to +3.6V
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time
may affect reliability.
16.2 3.3V DC Specifications
Symbol
Parameter
VDD, AVCC
Vih
Vil
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Vih
CMOS Input HIGH Voltage
Vil
CMOS Input LOW Voltage
Vipu
Input Pull-up Voltage
Iil
Input Leakage Current
Voh
Output HIGH Voltage
Vol
Output LOW Voltage
Voh
CMOS Output HIGH Voltage
Vol
CMOS Output LOW Voltage
Cin
Input Pin Capacitance
Cclk
CLK Pin Capacitance
CIDSEL IDSEL Pin Capacitance
Lpin
Pin Inductance
Condition
0 < Vin < VDD
Iout = –500µA
Iout = 1500µA
Iout = –500µA
Iout = 1500µA
Min.
3
0.5 VDD
-0.5
0.7 VDD
–0.5
0.7 VDD
0.9 VDD
VDD-0.5
5
Max.
3.6
VDD + 0.5
0.3 VDD
VDD + 0.5
0.3 VDD
Units Notes
3
V
1
±10
µA
3
0.1 VDD
V
0.5
2
10
12
pF
3
8
20
nH
Notes:
1. CMOS Input pins: S_CFN#, TCK, TMS, TDI, TRST#, SCAN_EN, SCAN_TM#
2. CMOS Output pin: TDO
3. PCI pins: P_AD[31:0], P_CBE[3:0], P_PAR, P_FRAME#, P_IRDY#, P_TRDY#, P_DEVSEL#, P_STOP#, P_LOCK#, PIDSEL#,
P_PERR#, P_SERR#, P_REQ#, P_GNT#, P_RESET#, S1_AD[31:0], S2_AD[31:0], S1_CBE[3:0], S2_CBE[3:0], S1_PAR,
S2_PAR, S1_FRAME#, S2_FRAME#, S1_IRDY#, S2_IRDY#, S1_TRDY#, S2_TRDY#, S1_DEVSEL#, S2_DEVSEL#,
S1_STOP#, S2_STOP#, S1_LOCK#, S2_LOCK#, S1_PERR#, S2_PERR#, S1_SERR#, S2_SERR#, S1_REQ[7:0]#,
S2_REQ[7:0]#, S1_GNT[7:0]#, S2_GNT[7:0], S1_RESET#, S2_RESET#, S1_EN, S2_EN, P_FLUSH#.
79
09/18/00 Rev 1.1