ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
13.2.31 Configuration Register 1 or 2: Bridge Control Register (bits 31-16; offset 3Ch)
Bit
Function
Type
Description
31-28 Reserved
R/O Reset to '0000'
27 Reserved
R/W Reset to 0
26 Master Timeout
Status
R/WC Set to '1' when either primary master or secondary master timeout.
Reset to 0
25 Reserved
R/W Reset to 0
24 Reserved
R/W Reset to 0
23 Fast Back-to-Back R/W Controls bridge's ability to generate fast back-to-back transactions to different
Enable
devices on the secondary interface.
0 = no fast back-to-back transaction
1 = enable fast back-to-back transacton
Reset to 0
22 Secondary Interface R/W Forces the assertion of S1_RESET# or S2_RESET# signal pin on the secondary
Reset
interface.
0 = do not force the assertion of S1_RESET# or S2_RESET# pin
1 = force the assertion of S1_RESET# or S2_RESET# pin
Reset to 0
21 Master Abort Mode R/W Controls bridge's behavior responding to master aborts on secondary interface.
0 = do not report master aborts (return FFFF_FFFFh on read and
discard data on write)
1 = report master aborts by signaling target abort if possible by the assertion of
P_SERR# if enabled
Reset to 0
20 Reserved
R/O Reset to 0
19 VGA Enable
R/W Controls the bridge's response to VGA compatible addresses.
0 = do not forward VGA compatible memory and I/O addresses
from primary to secondary
1 = forward VGA compatible memory and I/O address from primary to secondary
regardless of other settings
Reset to 0
18 ISA Enable
R/W Controls bridge's response to ISA I/O address which is limited to the first 64K.
0 = forward all I/O addresses in the range defined by the I/O Base and I/O
Limit registers,
1 = block forwarding of ISA I/O addresses in the range defined by the
I/O Base and I/O Limit registers that are in the first 64K of I/O space that address
the last 768 bytes in each 1 Kbytes block. Secondary I/O transactions are
forwarded upstream if the address falls within the
last 768 bytes in each 1 Kbyte block
Reset to 0
17 S1_SERR# or
S2_SERR#
Enable
Controls the forwarding of S1_SERR# or S2_SERR# to the primary interface.
0 = disable the forwarding S1_SERR# or S2_SERR# to primary
1 = enable the forwarding of S1_SERR# or S2_SERR# to primary interface.
Reset to 0
16 Parity Error
Response
Enable
Controls the bridge's response to parity errors on the secondary interface.
0 = ignore address and data parity errors on the secondary interface.
1 = enable parity error reporting and detection on the secondary interface.
Reset to 0
Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear.
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09/18/00 Rev 1.1