PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
13.2.32 Configuration Register 1 or 2: Diagnostic/Chip Control Register (bit 15-0, offset 40h)
Bit
Function Type
Description
15-11 Reserved
R/O Reset to '00000'
10-9 Test Mode
R/W Controls testability of chip's internal counters. When 00, all bits of counter are
exercised. When 01, byte 1 of counter is exercised. When 10, byte 2 of
counter is exercised. When 11, byte 3 of counter is exercised.
Reset to 0
8-5 Reserved
R/O Reset to '0000'
4 Reserved
R/W Reset to 0
3-2 Reserved
R/O Reset to '00'
1 Reserved
R/W Reset to 0
0 Reserved
R/O Reset to 0
13.2.33 Configuration Register 1 or 2: Arbiter Control Register (bit 31-16, offset 40h)
Bit
Function Type
Description
31:28 Reserved
R/O Reset to '0000'
27 Hybrid
R/W Mixed arbitration for masters from secondary bus 1 and 2.
0 = separate arbitration for S1_REQ[7:0]# and S2_REQ[7:0]#
1 = S1_REQ[3:0]# are mixed with S2_REQ[3:0]# for arbitration.
Only one arbiter is used.
Reset to 0
26 Reserved
R/W Reset to 0
25 Priority of
Secondary
Port
R/W Defines whether the secondary port of PI7C7100 is in high priority
group or the low priority group.
0 = low priority group
1 = high priority group
Reset to 1
24 Reserved
R/O Reset to 0
23-16 Arbiter
Control
R/W Each bit controls whether a secondary-bus master is assigned to the high priority
group or the low priority group. Bit [7:0] correspond to request inputs
S1_REQ[7:0]# or S2_REQ[7:0]#.
Reset to '00000000'
Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear.
64
09/18/00 Rev 1.1
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