ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
13.2.44 Configuration Register 2: Port Option Register (bit 15-0; offset74h)
Bit
Function
Type
Description
15-13 Reserved
R/O Reset to '000'
12 Reserved
R/W Reset to 0
11-10 Reserved
R/O Reset to '00'
9-8 Reserved
R/W Reset to '00'
7-6 Reserved
R/O Reset to '00'
5 ID Write Enable
R/W Allow write to Vendor ID, Device ID, Subsystem Vendor ID,
and Subsystem ID in the configuration space.
0 = Write protect
1 = Write enable
Reset to 0
4 Secondary MEMW
Command
Alias Enable
R/W Controls the bridge's detection mechanism for matching non-posted
memory write retry cycle from initiator on secondary interface.
0 = Command has to be exact
1 = MEMW is equivalent to MEMWI
Reset to 0
3 Secondary MEMR
Command
Alias Enable
R/W Controls the bridge's detection mechanism for matching memory
read retry cycle from initiator on secondary interface.
0=Command has to be exact
1=MEMR is equivalent to MEMRL or MEMRM
Reset to 0
2 Reserved
R/W Reset to 0
1 Reserved
R/W Reset to 0
0 Secondary
Pre Read
R/W Enable 1 more read for MEMR command on secondary.
0 = disable
1 = enable
Reset to 0
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09/18/00 Rev 1.1