PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
13.2.41 Config Register 1 or 2: Non-Posted Memory Base Register (read/write, bit 15-0; offset 70h)
This register defines the base address of the non-posted memory-mapped address range for forwarding the cycle through
the bridge. Upper twelve bits corresponding to address bits [31:20] are read/write. Lower 20 bits (19:0) are assumed to
be 00000h.
13.2.42 Config Register 1 or 2: Non-Posted Memory Limit Register (read/write, bit 31-16; offset 70h)
This register defines the upper limit address of the non-posted memory-mapped address range for forwarding the cycle
through the bridge. Upper twelve bits corresponding to address bits [31:20] are read/write. Lower 20 bits (19:0) are assumed
to be FFFFFh.
13.2.43 Configuration Register 1: Port Option Register (bit 15-0; offset74h)
Bit
Function
Type
Description
15-13
12
Reserved
Primary Pre Read
R/O Reset to '000'
Enable 1 more read for MEMR command on primary
R/W 1 = Enable
0 = No change
11-10
9
Reserved
Enable Long Request
Reset DTQUEUE
8
R/O Reset to '00'
Enable Long request for lock cycle
R/W 0 = No change
1 = Enable
Reset Secondary Delayed Transaction Queue
R/W 0 = No change
1 = Reset
7-6 Reserved
5 ID Write Enable
4 Secondary MEMW
Command Alias Enable
R/O Reset to '00'
R/W Allow write to Vendor ID, Device ID, Subsystem Vendor ID
and Subsystem ID in the configuration space.
0 = Write protect
1 = Write enable
Reset to 0
R/W Controls the bridge's detection mechanism for matching non-posted
memory write retry cycle from initiator on secondary interface.
0 = Command has to be exact
1 = MEMW is equivalent to MEMWI
Reset to 0
3 Secondary MEMR
Command Alias Enable
R/W Controls the bridge's detection mechanism for matching memory read
retry cycle from initiator on secondary interface.
0=Command has to be exact
1=MEMR is equivalent to MEMRL or MEMRM
Reset to 0
2 Primary MEMW
Command Alias Enable
R/W Controls the bridge's detection mechanism for matching non-posted
memory write retry cycle from initiator on primary interface.
0 = Command has to be exact
1 = MEMW is equivalent to MEMWI
Reset to 0
1 Primary MEMR
Command Alias Enable
0 Secondary
Pre Read
R/W Controls the bridge's detection mechanism for matching memory read
retry cycle from initiator on primary interface.
0 = Command has to be exact
1 = MEMR is equivalent to MEMRL or MEMRM
Reset to 0
R/W Enable 1 more read for MEMR command on secondary.
0 = disable
1 = enable
Reset to 0
67
09/18/00 Rev 1.1
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