PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
13.2.34 Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h)
This register is implemented but not being used internally.This register defines the base address of the primary
prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits
corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read
only and are set to 0h. The lower 20 address bits (19:0) are assumed to be 00000h.
13.2.35 Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h)
This register is implemented but not being used internally. The upper twelve bits corresponding to address bits [31:20]
are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h.
13.2.36 Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h)
This register is implemented but not being used internally.This register defines the upper limit address of the primary
prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits
corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read
only and are set to 0h. The lower 20 address bits (19:0) are assumed to be FFFFFh.
13.2.37 Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h)
This register is implemented but not being used internally. The upper twelve bits corresponding to address bits [31:20]
are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h.
13.2.38 Config Register 1 or 2: P_SERR# Event Disable Register (bit 7-0; offset 64h)
Bit
Function
Type
Description
7 Reserved
R/O Reset to 0
6 Delayed read - R/W Controls ability of PI7C7100 to assert P_SERR# when it is unable to transfer any
no data from
read data from the target after 224 attempts. P_SERR# is asserted if this event
target
occurs when this bit is 0 and SERR# enable bit in the command register is set.
Reset to 0
5 Delayed write
nondeliver
R/W Controls ability of PI7C7100 to assert P_SERR# when it is unable to transfer
delayed write data after 224 attempts. P_SERR# is asserted if this event occurs
when this bit is 0 and SERR# enable bit in the command register is set.
Reset to 0
4 Master abort
on posted
write
R/W Controls ability of PI7C7100 to assert P_SERR# when it receives a master abort
when attempting to deliver posted write data. P_SERR# is asserted if this event
occurs when this bit is 0 and SERR# enable bit in the command register is set.
Reset to 0
3 Target abort
during posted
write
R/W Controls ability of PI7C7100 to assert P_SERR# when it receives a target abort
when attempting to deliver posted write data. P_SERR# is asserted if this event
occurs when this bit is 0 and SERR# enable bit in the command register is set.
Reset to 0
2 Posted write
non-delivery
R/W Controls ability of PI7C7100 to assert P_SERR# when it is unable to deliver posted
write data after 224 attempts. P_SERR# is asserted if this event occurs when this bit
is 0 and SERR# enable bit in the command register is set.
Reset to 0
1 Posted write
parity error
R/W Controls ability of PI7C7100 to assert P_SERR# when a parity error is detected on
the target bus during a posted write transaction. P_SERR# is asserted if this event
occurs when this bit is 0 and SERR# enable bit in the command register is set.
Reset to 0
0 Reserved
R/O Reset to 0
Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear.
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09/18/00 Rev 1.1
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