PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
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Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
14. Bridge Behavior
A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a number of possibilities.
Those possibilities are summarized in the table below:
14.1 Bridge Actions for Various Cycle Types
Initiator
Target
Response
Master on primary
Target on Primary
PI7C7100 does not respond. It detects this situation by decoding
the address as well as monitoring the P_DEVSEL# for other fast
and medium devices on the primary port.
Master on primary
Target on secondary
PI7C7100 asserts P_DEVSEL#, terminates the cycle normally if it
is able to be posted, otherwise returns with a retry. It then passes
the cycle to the appropriate port. When the cycle is complete on the
target port, it will wait for the initiator to repeat the same cycle and
end with normal termination.
Master on primary
Target not on primary
nor secondary port
PI7C7100 does not respond and the cycle will terminate as master
abort.
Master on secondary Target on the same
secondary port
PI7C7100 does not respond.
Master on secondary
Target on primary or
the other secondary port
PI7C7100 asserts S1_DEVSEL# or S2_DEVSEL#, terminates the
cycle normally if it is able to be posted, otherwise returns with a
retry. It then passes the cycle to the appropriate port. When cycle is
complete on the target port, it will wait for the initiator to repeat the
same cycle and end with normal termination.
Master on secondary Target not on primary
nor the other secondary
PI7C7100 does not respond.
A target then has up to three cycles to respond before subtractive decoding is initiated. If the target detects an address
hit, it should assert its DEVSEL# signal in the cycle corresponding to the values of bits 9 and 10 in the Configuration Status
Register.
Termination of a PCI cycle can occur in a number of ways. Normal termination begins by the initiator (master)
de-asserting FRAME# with IRDY# being asserted (or remaining asserted) on the same cycle. The cycle
completes when TRDY# and IRDY# are both asserted simultaneously. The target should de-assert TRDY# for
one cycle following final assertion (sustained 3-state signal).
14.2 Transaction Ordering
To maintain data coherency and consistency, PI7C7100 complies with the ordering rules put forth in the PCI Local Bus
Specification, Rev 2.1. The following table summarizes the ordering relationship of all the transactions through the bridge.
PMW - Posted write (either memory write or memory write & invalidate)
DRR - Delayed read request (all memory read, I/O read & configuration read)
DWR - Delayed write request (I/O write & configuration write)
DRC - Delayed read completion (all memory read, I/O read & configuration read)
DWC - Delayed write completion (I/O write & configuration write )
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09/18/00 Rev 1.1
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