PIC16C505-04 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC16C505-04' PDF : 85 Pages View PDF
PIC16C505
FIGURE 10-7: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C505
VDD
MCLR
Internal
POR
32
DRT
Timeout
(Note 2)
Internal
RESET
Watchdog
Timer
RESET
I/O pin
(Note 1)
30
32
32
31
34
34
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT reset only in XT, LP and HS modes.
TABLE 10-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C505
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Parameter
No.
Sym
Characteristic
Min Typ(1) Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2000* — — ns VDD = 5.0 V
31
Twdt Watchdog Timer Time-out Period 9* 18* 30* ms VDD = 5.0 V (Commercial)
(No Prescaler)
32
TDRT Device Reset Timer Period(2)
9* 18* 30* ms VDD = 5.0 V (Commercial)
34
TioZ I/O Hi-impedance from MCLR Low — — 2000* ns
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
TABLE 10-6: DRT (DEVICE RESET TIMER PERIOD - PIC16C505
Oscillator Configuration
POR Reset
Subsequent Resets
IntRC & ExtRC
XT, HS & LP
18 ms (typical)
18 ms (typical)
300 µs (typical)
18 ms (typical)
© 1999 Microchip Technology Inc.
DS40192C-page 69
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