PIC18F010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I' PDF : 176 Pages View PDF
PIC18F010/020
CLRF
Clear f
Syntax:
[label] CLRF f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
000h → f
1→Z
Status Affected: Z
Encoding:
0110 101a ffff ffff
Description:
Clears the contents of the specified
register. If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Example:
CLRF
Before Instruction
FLAG_REG =
Z
=
After Instruction
FLAG_REG =
Z
=
FLAG_REG
0x5A
?
0x00
0
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD
Status Affected: TO, PD
Encoding:
0000 0000 0000 0100
Description:
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
Example:
CLRWDT
Before Instruction
WDT counter
=
WDT postscaler =
TO
=
PD
=
After Instruction
WDT counter
=
WDT postscaler =
TO
=
PD
=
?
?
?
?
0x00
0
1
1
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 111
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