PIC18F010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I' PDF : 176 Pages View PDF
CPFSGT
Compare f with WREG,
skip if f > WREG
Syntax:
[ label ] CPFSGT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (WREG),
skip if (f) > (WREG)
(unsigned comparison)
Status Affected: None
Encoding:
0110 010a ffff ffff
Description:
Compares the contents of data
memory location ’f’ to the contents
of the WREG by performing an
unsigned subtraction.
If the contents of ’f’ are greater than
the contents of , then the fetched
instruction is discarded and a NOP
is executed instead making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
1
Cycles:
1(2)
Note:3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ’f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
CPFSGT REG
NGREATER :
GREATER :
Before Instruction
PC
=
WREG
=
After Instruction
If REG
>
PC
=
If REG
≤
PC
=
Address (HERE)
?
WREG;
Address (GREATER)
WREG;
Address (NGREATER)
PIC18F010/020
CPFSLT
Compare f with WREG,
skip if f < WREG
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (WREG),
skip if (f) < (WREG)
(unsigned comparison)
Status Affected: None
Encoding:
0110 000a ffff ffff
Description:
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
If the contents of 'f' are less than
the contents of WREG, then the
fetched instruction is discarded and
a NOP is executed instead making
this a two-cycle instruction. If ’a’ is
0, the Access Bank will be
selected. If ’a’ is 1, the Bank will be
selected as per the BSR value.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ’f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
NLESS
LESS
CPFSLT REG
:
:
Before Instruction
PC
=
WREG
=
Address (HERE)
?
After Instruction
If REG
<
PC
=
If REG
≥
PC
=
WREG;
Address (LESS)
WREG;
Address (NLESS)
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 113
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