PIC18F010/020
7.0 8 X 8 HARDWARE MULTIPLIER
7.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F010/020 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 7-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 7-1: PERFORMANCE COMPARISON
Routine
Multiply Method
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Program
Memory
(Words)
13
1
33
6
21
24
52
36
Cycles
(Max)
69
1
91
6
242
24
254
36
Time
@ 40 MHz
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.4 µs
25.4 µs
3.6 µs
@ 10 MHz
27.6 µs
400 ns
36.4 µs
2.4 µs
96.8 µs
9.6 µs
102.6 µs
14.4 µs
@ 4 MHz
69 µs
1 µs
91 µs
6 µs
242 µs
24 µs
254 µs
36 µs
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 55