PIC18F010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I' PDF : 176 Pages View PDF
PIC18F010/020
7.2 Operation
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required,
when one argument of the multiply is already loaded in
the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MULWF
ARG1, WREG ;
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
EXAMPLE 7-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVFF
MULWF
BTFSC
SUBWF
MOVFF
BTFSC
SUBWF
ARG1, WREG
ARG2
ARG2, SB
PRODH
ARG2, WREG
ARG1, SB
PRODH
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Example 7-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
EQUATION 7-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 =
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 216)+
(ARG1H • ARG2L • 28)+
(ARG1L • ARG2H • 28)+
(ARG1L • ARG2L)
EXAMPLE 7-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MULWF
MOVFF
MOVFF
;
MOVFF
MULWF
MOVFF
MOVFF
;
MOVFF
MULWF
MOVFF
ADDWF
MOVFF
ADDWFC
CLRF
ADDWFC
;
MOVFF
MULWF
MOVFF
ADDWF
MOVFF
ADDWFC
CLRF
ADDWFC
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
PRODH, RES1 ;
PRODL, RES0 ;
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
PRODH, RES3 ;
PRODL, RES2 ;
ARG1L, WREG
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
PRODL, WREG ;
RES1
; Add cross
PRODH, WREG ; products
RES2
;
WREG
;
RES3
;
ARG1H, WREG ;
ARG2L
; ARG1H * ARG2L ->
; PRODH:PRODL
PRODL, WREG ;
RES1
; Add cross
PRODH, WREG ; products
RES2
;
WREG
;
RES3
;
Example 7-4 shows the sequence to do a 16 x 16
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 7-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
= ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216)+
(ARG1H • ARG2L • 28)+
(ARG1L • ARG2H • 28)+
(ARG1L • ARG2L)+
(-1 • ARG2H<7> • ARG1H:ARG1L • 216)+
(-1 • ARG1H<7> • ARG2H:ARG2L • 216)
DS41142A-page 56
Preliminary
2001 Microchip Technology Inc.
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