PIC18F010/020
FIGURE 8-1:
INTERRUPT LOGIC
T0IF
T0IE
T0IP
RBIF
RBIE
RBIP
INT0F
INT0E
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
XXXXIF
XXXXIE
XXXXIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
IPE
Additional Peripheral Interrupts
IPE
GIEL/PEIE
IPE
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
XXXXIF
XXXXIE
XXXXIP
Additional Peripheral Interrupts
T0IF
T0IE
T0IP
RBIF
RBIE
RBIP
Wake-up if in SLEEP mode
Interrupt to CPU
Vector to Location
0008h
GIEH/GIE
Interrupt to CPU
Vector to Location
0018h
GIEL\PEIE
DS41142A-page 60
Preliminary
2001 Microchip Technology Inc.